The present invention relates to a connecting structure, a printed substrate, a circuit, a circuit package and a method of forming a connecting structure. For example, the present invention relates to an electric circuit (e.g., an LSI (Large scale integrated circuit)) and a printed substrate (e.g., circuit substrate) and it relates to an electric circuit package (e.g., an LSI and a circuit substrate). For example, the present invention may be used suitably for portable electronic equipment (e.g., a mobile telephone which uses a battery as a power source and which is required for reducing power consumption).
When mounting an electric circuit (e.g., LSI) on a circuit substrate (or semiconductor chip) provided with surface electrodes for inputting/outputting signals, a wire bonding connection has been utilized. In this case, for example, since the length of the wire bonding is long, a problem may arise that the inductance, etc. may increase, thereby deteriorating RLC characteristics and making it difficult to input/output signals at high speed. Therefore, connection by a chip-on-board (or chip-on-chip) system of a flip-chip connection for an electric circuit (e.g., LSI) and a circuit substrate (or semiconductor chip) by way of bumps (protruded electrodes) has been utilized recently.
Electric circuits (e.g., LSIs) adopting a connection by the chip-on-board system of this type include, for example, those as shown in FIG. 7 of the related art.
As shown in FIG. 7, electric circuit (e.g., LSI 1) 1 has a plurality of layers or pads (surface electrodes) 2, . . . , 2 for inputting/outputting signals disposed at predetermined positions, and has solder bumps 5, . . . , 5 for flip-chip connection to a printed substrate 4 having a plurality of pads (surface electrodes) 3, . . . , 3 for inputting/outputting signals at the positions corresponding to pads 2, . . . , 2. In this case, pads 2, . . . , 2 and pads 3, . . . 3 are formed, for example, each into a circular post of 1 mm diameter, and the distance between pads 2, . . . , 2 and pads 3, . . . , 3 (that is, a height for solder bump 5) is set to 10 μm. Further, solder bumps 5, . . . , 5 each have a substantially spherical shape.
FIG. 8 is an exemplary circuit diagram showing the electrical constitution of a main portion of the printed substrate 4 connected by flip-chip connection with electric circuit 1 (e.g., LSI 1) in FIG. 7.
In printed substrate 4, as shown in FIG. 8, one of the terminals of capacitive part 12 and one of the terminals of resistive part 13 are connected by transmission channel (pattern) 11 to pad 3, and the other of the terminals of capacitive part 12 and the other of the terminals of resistive part 13 are connected to ground (GND). Transmission channel 11 has, for example, a characteristic impedance of 100Ω, a transmission delay time of 7.5 ns/m, and a wire length of 50 cm. Further, the capacitance of capacitive part 12 is 20 pF and the resistance value of resistive part 13 is 100Ω.
FIG. 9 is an exemplary graph showing an exemplary embodiment of a measured value for a consumption current of an output buffer (not illustrated) used as an interface on an output side of electric circuit 1 (e.g., LSI 1) in FIG. 8 in which a current value is expressed on the ordinate and time is expressed on the abscissa.
As shown in FIG. 9, for example, the current value is −12 mA as the minimum value and 19.5 mA as the maximum value, and the difference between them is 31.5 mA.
In addition to the electric circuit (e.g., LSI) described above, the techniques of this type include, for example, those as described in the following document.
That is, bypass capacitor described in JP-A No. 102432/1997 includes a dielectric material interposed between grid array type electronic parts and a printed substrate, and connected with the power source electrode and the grounded electrode. Accordingly, inductance relative to the electronic part is eliminated, thereby to make the power supply to the electronic part efficient. Further, the electronic part and the printed substrate are connected by way of an electrode for mounting to the substrate.